1. Field of the Invention
The present invention relates to a record medium and a data transferring method using a nonvolatile memory suitable for an IC card having a flash memory suitable for storing music data and picture data, in particular, to those that allow a data transfer rate against a host device to be improved and a circuit scale to be reduced.
2. Description of the Related Art
As a storage device that stores music data and picture data disclosed in for example Japanese Patent Laid Open Publication No. 7-311708, an IC card having a flash memory is becoming attractive. The flash memory is a nonvolatile memory that is composed of memory cell transistors each of which has a floating gate. Such an IC card comprises a memory cell array, a controller, an interface packaged in a card shaped case. The controller controls read/write processes for data from/to the memory cell array. The interface inputs and outputs data to/from a host side device. When data is transferred to the host device, CRC (Cyclic Redundancy Code) is added to the data so as to correctly transfer data to the host device and detect an error. In a NAND type flash memory, data is accessed page by page. Thus, CRC code is generated page by page. When an error is detected using the CRC code, the data re-transfer process is performed.
In FIG. 1, reference numeral 101 is an IC card. Reference numeral 102 is a host device. The IC card 101 comprises a NAND type flash memory cell array. Examples of the host device 102 are a personal computer, a digital camera, a digital audio player, and a portable terminal unit. The host device 102 and the IC card 101 are connected through a transfer path 103.
The host device 102 may have a card holding portion. By attaching the IC card 101 to the card holding portion, the IC card 101 is connected to the host device 102. Alternatively, a drive device for the IC card 101 may be disposed. In this case, the IC card 101 is attached to the drive device. The host device 102 is connected to the IC card 101 through the drive device using a cable or a radio wave.
As shown in FIG. 2, the IC card 101 comprises a memory cell array 111, a controller 112, and an interface 113. The controller 112 controls the read process of the memory cell array 111. The interface 113 inputs and outputs data to/from the host side device. A data latch 115 is disposed in association with the memory cell array 111. The controller 112 comprises a shift register 116 and a CRC calculating circuit 117. The shift register 116 has a storage capacity for data of one page.
As shown in FIG. 3, the memory cell array 111 is composed of NAND strings. Each NAND string is composed of memory cell transistors each having a floating gate. For example, each NAND string is composed of for example 16 memory cell transistors MT0 to MT15 that are tandem connected and selection gate transistors SG1 and SG2 are connected to the drain side and the source side of the memory cell transistors MT0 to MT15, respectively.
The drains of the drain side selection gate transistors SG1, SG1, and so forth are connected to bit lines BL1, BL2, and so forth, respectively. The sources of the source side selection gate transistors SG2, SG2, and so forth are connected to a source line Vs.
The gates of the memory cell transistors disposed in the line direction are connected to common word lines WL0, WL1, and W15, respectively. The gate of the selection gate transistor SG1 is connected to a control signal line DSG. The gate of the selection gate transistor SG2 is connected to a control signal line SSG. The word lines WL0 to WL15 and the control signal lines DSG and SSG are connected to row decoders (not shown). Memory cell transistors connected to the same word lines WL0, WL1, and WL15 compose a page. The bit lines BL1, BL2, and so forth are connected to the data latch 115.
In FIG. 2, when data that is read from the IC card 101 is transferred to the host device 102 side, data for one page is accessed from the memory cell array 111 of the IC card 101. The data for one page is latched to the data latch 115. The data for one page is transferred to the shift register 116 for a data re-transfer process for data to the host device 102 in the case that a transfer error takes place.
The data transferred to the shift register 116 is sent to the host device 102 side through the CRC calculating circuit 117, the interface 113, and the transfer path 103. The data is sent from an interface 123 on the host device 102 side to the memory 124 through a CRC calculating circuit 122 and a data bus 125.
When the data for one page is transferred from the IC card 101 to the host device 102, the CRC code generated in the CRC calculating circuit 117 is sent to the host device 102 side.
The CRC calculating circuit 122 on the host device 102 side performs a CRC calculation using the received data and the CRC code and determines whether an error of the received data takes place. When the CRC calculating circuit 122 does not detect an error of the received data, as described above, data for the next page is read from the memory cell array 111 and transferred from the IC card 101 to the host device 102.
When an error is detected, the host device 102 sends a data re-transfer request to the IC card 101.
When the IC card 101 receives the data re-transfer request, the IC card 101 performs the data re-transfer process. In the data re-transfer process, data for one page stored in the shift register 116 is transferred to the host device 102 side through the transfer path 103. After the data for one page has been transferred, the CRC code generated in the CRC calculating circuit 117 is sent to the host device 102 side.
The CRC calculating circuit 122 on the host device 102 side performs the CRC calculation using the received data and the CRC code and determines whether or not an error of the received data takes place. When the CRC calculating circuit 122 does not detect an error of the received data, as described above, data for the next page is read from the memory cell array 111 and transferred from the IC card 101 to the host device 102
FIGS. 4A to 4D and 5A to 5D are timing charts showing data transferred from the IC card 101 to the host device 102. FIGS. 4A to 4D show the operation in the case that a transfer error does not take place.
FIGS. 5A to 5D show the operation in the case that a transfer error takes place.
First of all, the operation in the case that a transfer error does not take place will be described.
In FIG. 4A, a signal RD is a signal that is internally generated corresponding to a read instruction to the memory cell array 111. The signal RD causes a first access operation to be active. This instruction causes data for one page to be read from the memory cell array 111 and latched to the data latch 115.
As shown in FIG. 4A, from time tg00 to time tg01, the signal level of the signal RD becomes high. As a result, data D0 for one page is read from the memory cell array 111. As shown in FIG. 4B, at time tg01, the data D0 is latched to the data latch 115.
From time tg01 to time tg02, the data D0 is transferred from the data latch 115 to the shift register 116.
From time tg02 to time tg04, the data D0 is transferred from the shift register 116 to the host device 102. After the data D0 for one page has been transferred, the CRC code is generated in the CRC calculating circuit 117. The CRC code is transferred to the host device 102 side.
In addition, from time tg02 to time tg03, the signal level of the signal RD becomes high. As a result, data for the next page is read from the memory cell array 111. At time tg03, the data D1 is latched to the data latch 115.
At time tg04, the data D0 for one page has been transferred. After the CRC code has been transferred, the CRC calculating circuit 122 of the host device 102 performs the CRC calculation and detects an error of the received data.
When the CRC calculating circuit 122 does not detect an error of the data D0, from time tg04 to time tg05, the data D1 is transferred from the data latch 115 to the shift register 116.
From time tg05 to time tg07, the data D1 is transferred from the shift register 116 to the host device 102. After the data D1 for one page has been transferred, the CRC code generated in the CRC calculating circuit 117 is transferred to the host device 102 side.
In addition, as shown in FIG. 4A, from time tg05 to time tg06, the signal level of the signal RD becomes high. As a result, data D2 of the next page is read from the memory cell array 111. As shown in FIG. 4B, at time tg06, the data D2 is latched to the data latch 115.
Thereafter, the same operation is repeated.
FIGS. 5A to 5D show the operation in the case that a transfer error is detected.
As shown in FIG. 5A, from time th00 to time th01, the signal level of the signal RD becomes high. As a result, data D0 for one page is read from the memory cell array 111. As shown in FIG. 5B, at time th01, the data D0 is latched to the data latch 115.
As shown in FIG. 5C, from time th01 to time th02, the data D0 is transferred from the data latch 115 to the shift register 116.
From time th02 to time th04, the data D0 is transferred from the shift register 116 to the host device 102. After the data D0 for one page has been transferred, the CRC code generated in the CRC calculating circuit 117 is transferred to the host device 102 side.
In addition, from time th02 to time th03, the signal level of the signal RD becomes high. As a result, data for the next page is read as data D1 from the memory cell array 111.
After the data D0 for one page has been transferred and then the CRC code has been transferred at time th04, the CRC calculating circuit 122 of the host device 102 performs the CRC calculation and detects an error of the data D0.
When the CRC calculating circuit 122 detects an error of the data D0, as shown in FIG. SD, from time th04 to time th05, the data D0 is transferred from the shift register 116 to the host device 102. After the data D0 for one page has been transferred, the CRC code generated in the CRC calculating circuit 117 is transferred to the host device 102 side. The host device 102 detects an error of the data D0. When the host device 102 does not detect an error of the data D0, as shown in FIG. 5C, from time th05 to time th06, the data D1 is transferred from the data latch 115 to the shift register 116.
Thereafter, the same operation is repeated.
Thus, conventionally, when data is transferred from the IC card 101 to the host device 102, for the data re-transfer process for data in the case that a transfer error takes place, while data for each page that has been read from the memory cell array 111 is stored in the shift register 116, the data is transferred from the IC card 101 to the host device 102.
In this case, when successive pages are read, the first access operation is recognized only for the first page, not other pages because the first access operation is performed while data is being transferred. Thus, when the size of one page is 512 bytes; the bus width is 8 bits; the number of bytes of the CRC code is 10 bytes; the frequency of the synchronous clock for transferring data from the IC card 101 to the host device 102 is 20 MHz; and the internal transfer rate from the data latch 115 to the shift register 116 is 20 MHz, then time necessary for outputting data for one page is expressed as follows.
50 nsecxc3x97(512+522)=51.7 isec 
Thus, the data transfer rate becomes 9.9 Mbytes/sec.
In the example shown in FIG. 2, for the data re-transfer process in the case that a transfer error takes place, data for one page that has been read from the memory cell array 111 is transferred from the data latch 115 to the shift register 116. Thereafter, the data is transferred to the host device 102 side through the transfer path 103. In this case, the data transfer time for data transferred from the data latch 115 to the shift register 116 and the data transfer time for data transferred from the shift register 116 to the host device 102 are required.
In addition, in the NAND flash memory, one page is divided into a first half area and a second half area. While the first half area is being transferred, the second half area is firstly accessed. When a plurality of pages are successively accessed, high speed read process is performed free of time for the first access operation. In other words, so-called gapless read process has been proposed (for example, Japanese Patent Laid Open Publication No. 9-106689).
However, conventionally, in the structure of which while an error is being detected using CRC code, data for each page is transferred, the gadless read process cannot be accomplished.
In addition, in the structure shown in FIG. 2, for the data re-transfer process, data received from the data latch 115 should be stored in the shift register 116. Conventionally, since data for each page is read from the shift register 116, the shift register 116 should have a storage capacity for data of one page.
Conventionally, the data amount of one page is 512 bytes. However, as the storage capacity of the flash memory increases, it is expected that the page size increases. Thus, since a conventional IC card requires a shift register having the storage capacity for one page, as the page size increases, the circuit scale adversely becomes large.
An object of the present invention is to provide a record medium and a data transferring method for use with a card system for reading data page by page and detecting an error of the data using a nonvolatile memory that allow a data re-transfer process to be performed in the case that a transfer error takes place and that allow the data transfer rate of a data transfer process including a data re-transfer process to become high.
Another object of the present invention is to provide a record medium and a data transfer method for use with a card system using a nonvolatile memory that allow data to be gaplessly read unless a transfer error is detected and that allow data to be re-transferred at high speed even if data is re-transferred in the case that a transfer error takes place.
A further object of the present invention is to provide a record medium and a data transfer method using a nonvolatile memory that allow the storage capacity of a shift register for a data re-transfer process to become small.
A first aspect of the present invention is a record medium composed of a nonvolatile memory, the nonvolatile memory having a nonvolatile memory cell array that is accessible page by page, a controlling portion for controlling the nonvolatile memory cell array, and an input/output portion for connecting the nonvolatile memory to an external device, the record medium comprising a latching means for latching data for one page that is read from the memory cell array, a shift register for storing data that is output from the latching means for a data re-transfer process in the case that a transfer error is detected, a switching means for switching between output data of the latching means and output data of the shift register, and a controlling means for transferring data for each page that is output from the memory cell array through the switching means to the external device through the input/output portion, determining whether or not a transfer error takes place in the transferred data, and performing the data re-transfer process for the data when a transfer error takes place in the transferred data, wherein when the transfer error does not take place in the transferred data, the switching means is controlled so that output data of the latching means is transferred to the external device, and wherein when the transfer error takes place in the transferred data and the data re-transfer process is performed for the transferred data, the switching means is controlled so that the data for one page stored in the shift register is transferred to the external device.
A second aspect of the present invention is a record medium composed of a nonvolatile memory, the nonvolatile memory having a nonvolatile memory cell array that is accessible page by page, a controlling portion for controlling the nonvolatile memory cell array, and an input/output portion for connecting the nonvolatile memory to an external device, the record medium comprising a first latching means for latching data of the first half area of one page read from the memory cell array, a second latching means for latching data of the second half area of one page read from the memory cell array, a controlling means for controlling a read process of the memory cell array in such a manner that while data of the first half area of one page or data of the second half area of one page is being transferred, data of the second half area of one page or data of the first half area of one page is accessed, a first shift register for storing data that is output from the first latching means for a data re-transfer process in the case that a transfer error is detected, a second shift register for storing data that is output from the second latching means for the data re-transfer process in the case that a transfer error is detected, a switching means for switching between output data of the first latching means and the second latching means and output data of the first shift register and the second shift register, and a controlling means for transferring data for each page that is output from the memory cell array through the switching means to the external device through the input/output portion, determining whether or not a transfer error takes place in the transferred data, and performing the data re-transfer process for the data when a transfer error takes place in the transferred data, wherein when the transfer error does not take place in the transferred data, the switching means is controlled so that output data of the first latching means and the second latching means is transferred to the external device, and wherein when the transfer error takes place in the transferred data and the data re-transfer process is performed for the transferred data, the switching means is controlled so that the data of the first half area of one page stored in the first shift register and the data of the second half area of one page stored in the second shift register are transferred to the external device.
A third aspect of the present invention is a record medium composed of a nonvolatile memory, the nonvolatile memory having a nonvolatile memory cell array that is accessible page by page, a controlling portion for controlling the nonvolatile memory cell array, and an input/output portion for connecting the nonvolatile memory to an external device, the record medium comprising a first latching means for latching data of the first half area of one page read from the memory cell array, a second latching means for latching data of the second half area of one page read from the memory cell array, a controlling means for controlling a read process of the memory cell array in such a manner that while data of the first half area of one page or data of the second half area of one page is being transferred, data of the second half area of one page or data of the first half area of one page is accessed, a shift register for storing data that is read from the first latching means for a data re-transfer process in the case that a transfer error is detected, a switching means for switching between output data of the first latching means and the second latching means and output data of the shift register, and a controlling means for transferring data for each page that is output from the memory cell array through the switching means to the external device through the input/output portion, determining whether or not a transfer error takes place in the transferred data, and performing the data re-transfer process for the data when a transfer error takes place in the transferred data, wherein when the transfer error does not take place in the transferred data, the switching means is controlled so that output data of the first latching means and the second latching means is transferred to the external device, and wherein when the transfer error takes place in the transferred data and the data re-transfer process is performed for the transferred data, the switching means is controlled so that the data of the first half area of one page stored in the shift register and the data of the second half area of one page stored in the second latching means are transferred to the external device.
The data for one page may be unequally divided into data of the first half area of one page and data of the second half area of one page.
A fourth aspect of the present invention is a data transferring method, comprising the steps of accessing data for one page from a memory cell array and latching the data for one page to a latching means, transferring the data for one page from the latching means to an external device and storing the data for one page to a shift register for a data re-transfer process in the case that a transfer error is detected, determining whether or not a transfer error takes place in the data for one page transferred from the latching means to the external device, transferring data for the next page to the external device when the transfer error is not detected, and transferring the data for one page stored in the shift register to the external device when the transfer error is detected.
A fifth aspect of the present invention is a data transferring method for a record medium composed of a flash memory for dividing a nonvolatile memory cell array that is accessible page by page into a first half area of one page and a second half area of one page and performing a gapless read process in such a manner that while data of the first half area of one page or data of the second half area of one page is being transferred, data of the second half area of one page or data of the first half area of one page is accessed, the method comprising the steps of accessing the data of the first half area of one page from the memory cell array and latching the data of the first half area of one page to a first latching means, transferring the data of the first half area of one page from the first latching means to an external device, storing the data of the first half area of one page to a first shift register for a data re-transfer process in the case that a transfer error is detected, accessing the data of the second half area of one page from the memory cell array, and latching the data of the second half area of one page to a second latching means, after the data of the first half area of one page has been transferred, transferring the data of the second half area of one page to the external device, storing the data of the second half area of one page to a second shift register for a data re-transfer process in the case that a transfer error is detected, and accessing data of the first half area of the next page from the memory cell array, after the data of the first half area of one page and the data of the second half area of one page have been transferred to the external device, determining whether or not a transfer error takes place in the data for one page transferred to the external device, when the transfer error is not detected, reading and transferring data for the next page, and when the transfer error is detected, transferring the data of the first half area of one page stored in the first shift register to the external device and transferring the data of the second half area of one page stored in the second shift register to the external device.
A sixth aspect of the present invention is a data transferring method for a record medium composed of a flash memory for dividing a nonvolatile memory cell array that is accessible page by page into a first half area of one page and a second half area of one page and performing a gapless read process in such a manner that while data of the first half area of one page or data of the second half area of one page is being transferred, data of the second half area of one page or data of the first half area of one page is accessed, the method comprising the steps of accessing the data of the first half area of one page from the memory cell array and latching the data of the first half area of one page to a first latching means, transferring the data of the first half area of one page from the first latching means to an external device, storing the data of the first half area of one page to a shift register for a data re-transfer process in the case that a transfer error is detected, accessing the data of the second half area of one page from the memory cell array, and latching the data of the second half area of one page to a second latching means, after the data of the first half area of one page has been transferred, transferring the data of the second half area of one page to the external device and accessing data of the first half area of the next page from the memory cell array, after the data of the first half area of one page and the data of the second half area of one page have been transferred to the external device, determining whether or not a transfer error takes place in the data for one page transferred to the external device, when the transfer error is not detected, transferring data for the next page, and when the transfer error is detected, transferring the data of the first half area of one page stored in the first shift register to the external device and transferring the data of the second half area of one page latched in the second latching means to the external device.
The data for one page may be unequally divided into data of the first half area of one page and data of the second half area of one page.
When data is not gaplessly read, a shift register and a switching circuit are disposed. The shift register stores data for one page for the data re-transfer process in the case that a transfer error takes place. The switching circuit switches between output data of a memory cell array and output data of the shift register depending on whether or not a transfer error takes place. When a transfer error does not take place, output data of the memory cell array is directly transferred. On the other hand, when a transfer error takes place, output data of the shift register is transferred. As a result, data can be transferred between the IC card and the host device at the logically maximum speed.
When data is gaplessly read, while data of the first half area of one page or data of the second half area of one page is being transferred, data of the second half area of one page or data of the first half area of one page is being firstly accessed to the memory cell array. As a result, data can be gaplessly read. In this case, a first shift register, a second shift register, and a switching circuit are disposed. The first shift register stores data of the first half area of one page for the data re-transfer process in the case that a transfer error takes place. The second shift register stores data of the second half area of one page for the data re-transfer process in the case that a transfer error takes place. The switching circuit switches between output data of the memory cell array and output data of the first and second shift registers. When a transfer error does not take place, the output data of the memory cell array is transferred. When a transfer error takes place, output data of the first and second shift registers is transferred. As a result, when data is transferred between the IC card and the host device, data can be gaplessly read at the logically maximum speed.
In addition, data of the second half area of one page is re-transferred from a data latch. As a result, the storage capacity of the shift register can be reduced to the half of one page.
In addition, one page is unequally divided. As a result, the storage capacity of the shift register can be reduced to less than the half of one page.